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CY62177EV18 mobl ? 32-mbit (2 m 16 / 4 m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-76091 rev. *c revised november 28, 2014 32-mbit (2 m 16 / 4 m 8) static ram features thin small outline package (tsop) i configurable as 2 m 16 or as 4 m 8 static ram (sram) very high speed ? 70 ns wide voltage range ? 1.65 v to 2.25 v ultra low standby power ? typical standby current: 3 ? a ? maximum standby current: 25 ? a ultra low active power ? typical active current: 4.5 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2, and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 48-ball tsop i and 48-ball fbga package functional description the CY62177EV18 is a high-performance cmos static ram organized as 2 m words by 16 bits and 4 m words by 8 bits. this device features advanced circuit design to provide ultra low active current. it is ideal for providing more battery life ? (mobl ? ) in portable applications, such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power c onsumption by 99 percent when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location spec ified on the address pins (a 0 through a 20 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written to the location specified on the address pins (a 0 through a 20 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. pin #13 of the 48 tsop i pack age is an dnu pin that must be left floating at all times to ensure proper application . for a complete list of related documentation, click here . i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 0 a 1 a 9 a 10 power- down circuit bhe ble ce 2 ce 1 ce 2 ce 1 byte column decoder a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 20 2m 16 ram array logic block diagram
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 2 of 17 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community ................................. 17 technical support ................. .................................... 17
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 3 of 17 pin configuration figure 1. 48-pin tsop i pinout (front view) [1, 2] figure 2. 48-ball fbga pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we ce2 dnu bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a21 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce1 a0 we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 a 20 3 2 6 5 4 1 d e b a c f g h a 16 nc vcc product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max CY62177EV18ll 1.65 1.8 2.25 70 4.5 5.5 35 45 3 25 notes 1. dnu pin# 13 needs to be left floating to ensure proper application. 2. the byte pin in the 48-tsop i package has to be tied to v cc to use the device as a 2 m 16 sram. the 48-pin tsop i package can also be used as a 4 m 8 sram by tying the byte signal to v ss . in the 4 m 8 configuration, pin 45 is a21, while bhe , ble, and i/o 8 to i/o 14 pins are not used. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 4 of 17 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential ....................................... ?0.2 v to v cc(max) + 0.2 v dc voltage applied to outputs in high z state [4, 5] .......................?0.2 v to v cc(max) + 0.2 v dc input voltage [4, 5] .................... ?0.2 v to v cc(max) + 0.2 v output current into outputs (low) ............................. 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current ..................................................... > 200 ma operating range device range ambient temperature v cc [6] CY62177EV18ll industrial ?40 c to +85 c 1.65 v to 2.25 v electrical characteristics over the operating range parameter description test conditions 70 ns unit min typ [7] max v oh output high voltage i oh = ?0.1 ma v cc = 1.65 v 1.4 ? ? v v ol output low voltage i ol = 0.1 ma v cc = 1.65 v ? ? 0.2 v v ih input high voltage v cc = 1.65 v to 2.25 v 1.4 ? v cc + 0.2 v v v il [8] input low voltage v cc = 1.65 v to 2.25 v ?0.2 ? 0.4 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?3545ma f = 1 mhz ? 4.5 5.5 ma i sb2 [9, 10] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?325 ? a notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 8. under dc conditions the device meets a v il of 0.8 v. however, in dynamic conditions input low voltage applied to the device must not be higher than 0.7 v. 9. the byte pin in the 48-tsop i package has to be tied to v cc to use the device as a 2 m 16 sram. the 48-ts op i package can also be used as a 4 m 8 sram by tying the byte signal to v ss . in the 4 m 8 configuration, pin 45 is a21, while bhe , ble, and i/o 8 to i/o 14 pins are not used. 10. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating.
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 5 of 17 capacitance parameter [11] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 15 pf c out output capacitance 15 pf thermal resistance parameter [11] description test conditions fbga tsopi unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, 2-layer printed circuit board 38.10 44.66 ? c/w ? jc thermal resistance (junction to case) 7.54 12.12 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 table 1. ac test loads parameters value unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v note 11. tested initially and after any design or proc ess changes that may affect these parameters.
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 6 of 17 data retention characteristics over the operating range parameter description conditions min typ [12] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [13] data retention current v cc = 1.0 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ??17 ? a t cdr [14] chip deselect to data retention time 0??ns t r [15] operation recovery time 70 ? ? ns data retention waveform figure 4. data retention waveform [16] t cdr v dr > 1.0 v data retention mode t r ce 1 or v cc bhe . ble or v cc(min) v cc(min) ce 2 notes 12. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 13. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 14. tested initially and after any design or process changes that may affect these parameters. 15. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 16. bhe .ble is the and of both bhe and ble . chip is deselected by either disabling the chip enable signals or by disabling both bhe and ble .
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 7 of 17 switching characteristics over the operating range parameter [17, 18] description 70 ns unit min max read cycle t rc read cycle time 70 ? ns t aa address to data valid ? 70 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 70 ns t doe oe low to data valid ? 35 ns t lzoe oe low to low z [19] 5 ? ns t hzoe oe high to high z [19, 20] ? 25 ns t lzce ce 1 low and ce 2 high to low z [19] 10 ? ns t hzce ce 1 high and ce 2 low to high z [19, 20] ? 25 ns t pu ce 1 low and ce 2 high to power up 0 ? ns t pd ce 1 high and ce 2 low to power down ? 70 ns t dbe ble/bhe low to data valid ? 70 ns t lzbe ble /bhe low to low z [19] 10 ? ns t hzbe ble /bhe high to high z [19, 20] ? 25 ns write cycle [21, 22] t wc write cycle time 70 ? ns t sce ce 1 low and ce 2 high to write end 60 ? ns t aw address setup to write end 60 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 45 ? ns t bw ble /bhe low to write end 60 ? ns t sd data setup to write end 30 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [19, 20] ? 25 ns t lzwe we high to low z [19] 10 ? ns notes 17. test conditions for all parameters other than tristate parame ters assume signal transition time of 1 v/ns, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in table 1 on page 5 . 18. in an earlier revision of this device, under a specific application condition, read and write operations were limited to swi tching of the byte enable and/or chip enable signals as described in the application notes an13842 and an66311 . however, the issue has been fixed and in prod uction now, and hence, these application notes are no longer applicable. they are available for download on our w ebsite as they contain information on the date code of the pa rts, beyond which the fix has been in production. 19. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 20. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedence state. 21. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a writ e by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 22. the minimum write cycle pulse width for write cycle no. 3 (we controlled, oe low) should be equal to the sum of t sd and t hzwe .
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 8 of 17 switching waveforms figure 5. read cycle 1 (address transition controlled) [23, 24] figure 6. read cycle 2 (oe controlled) [24, 25] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe high i cc i sb impedance oe ce 1 address v cc supply current bhe / ble data out ce 2 notes 23. the device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 24. we is high for read cycle. 25. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high.
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 9 of 17 figure 7. write cycle 1 (we controlled) [26, 27, 28, 29] figure 8. write cycle 2 (ce 1 or ce 2 controlled) [26, 27, 28, 29] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 29 address we data i/o oe bhe / ble ce 1 ce 2 t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data note 29 t bw t sa address we data i/o oe bhe / ble ce 1 ce 2 notes 26. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inacti ve. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 27. data i/o is high impedance if oe = v ih . 28. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high-impedance state. 29. during this period the i/os are in output state and input signals should not be applied.
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 10 of 17 figure 9. write cycle 3 (we controlled, oe low) [30, 31, 32] figure 10. write cycle 4 (bhe /ble controlled, oe low) [30, 32] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 31 address ce 1 ce 2 bhe / ble we data i/o t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 31 address ce 1 ce 2 bhe / ble we data i/o notes 30. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high-impedance state. 31. during this period the i/os are in output state and input signals should not be applied. 32. the minimum write cycle pulse width should be equal to the sum of t sd and t hzwe .
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 11 of 17 truth table ce 1 ce 2 we oe bhe ble inputs outputs mode power hx [33] x x x x high z deselect/power down standby (i sb ) x [33] l x x x x high z deselect/power down standby (i sb ) x [33] x [33] x x h h high z deselect/power down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l high z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) lhhllhdata out (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) read active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l high z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) write active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) note 33. the ?x? (don?t care) state for the chip enables in the truth table refer to the logic state (either high or low). intermedia te voltage levels on these pins is not permitted.
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 12 of 17 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 70 CY62177EV18ll-70baxi 51-85191 48 ball fbga (8 9.5 1.2 mm) pb-free industrial contact your local cypress sales repres entative for availability of these parts. z = 48tsop i, ba = 48 ball fbga temperature grade: i = industrial x = pb-free package type: speed grade: 70 ns low power voltage range: v18 = 1.8 v (typical) process technology: e = 90 nm bus width = 16 density = 32-mbit 621 = mobl sram family company id: cy = cypress 621 cy 7 v18 - 70 z,ba i x ll e 7
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 13 of 17 package diagrams figure 11. 48-ball fbga (8 9.5 1.2 mm) package outline, 51-85191 51-85191 *c
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 14 of 17 figure 12. 48-pin tsop i (12 18.4 1.0 mm) package outline, 51-85183 package diagrams (continued) 51-85183 *c
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 15 of 17 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad ps picosecond vvolt wwatt
CY62177EV18 mobl ? document number: 001-76091 rev. *c page 16 of 17 document history page document title: CY62177EV18 mobl ? , 32-mbit (2 m 16 / 4 m 8) static ram document number: 001-76091 revision ecn orig. of change submission date description of change ** 3528465 aju 02/17/2012 new data sheet. *a 4116295 memj 09/10/2013 changed stat us from preliminary to final. updated features : added 48-ball fbga package related information. updated ordering information (updated part numbers). updated package diagrams : spec 51-85191 ? changed revision from *b to *c. updated in new template. *b 4301112 nile 03/07/2014 updated switching characteristics : added note 18 and referred the same note in ?parameter? column. completing sunset review. *c 4571881 nile 11/28/2014 added related documentation hyperlink in page 1. added note 22 in switching characteristics . added note reference 22 in the switching characteristics table. added note 32 in switching waveforms . added note reference 32 in figure 9 .
document number: 001-76091 rev. *c revised november 28, 2014 page 17 of 17 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademarks of their respective holders. CY62177EV18 mobl ? ? cypress semiconductor corporation, 2012-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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